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| 74VHC595 8-Bit Shift Register with Output Latches May 2007 74VHC595 8-Bit Shift Register with Output Latches Features High Speed: tPD = 5.4ns (Typ.) at VCC = 5V Low power dissipation: ICC = 4A (Max.) at TA = 25C High noise immunity: VNIH = VNIL = 28% VCC (Min.) Power down protection is provided on all inputs Low noise: VOLP = 0.9V (Typ.) Pin and function compatible with 74HC595 tm General Description The VHC595 is an advanced high-speed CMOS Shift Register fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has eight 3-STATE outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output (standard) pins for cascading. Both the shift register and storage register use positive-edge triggered clocks. If both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Information Order Number 74VHC595M 74VHC595SJ 74VHC595MTC Package Number M16A M16D MTC16 Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering number. (c)1993 Fairchild Semiconductor Corporation 74VHC595 Rev. 1.2 www.fairchildsemi.com 74VHC595 8-Bit Shift Register with Output Latches Connection Diagram Logic Symbol IEEE/IEC Pin Description Pin Names SER SCK RCK SCLR G QA - QH Q'H Description Serial Data Input Shift Register Clock Input (Active rising edge) Storage Register Clock Input (Active rising edge) Reset Input 3-STATE Output Enable Input (Active LOW) Parallel Data Outputs Serial Data Output Truth Table Inputs SER X X X L H X RCK X X X X X SCK X X X X SCLR X X L H H H G H L L L L L QA thru QH 3-STATE Function QA thru QH outputs enabled Shift Register cleared: QH = 0 Shift Register clocked: QN = Qn-1, Q0 = SER = L Shift Register clocked: QN = Qn-1, Q0 = SER = H Contents of Shift Register transferred to output latches (c)1993 Fairchild Semiconductor Corporation 74VHC595 Rev. 1.2 www.fairchildsemi.com 2 74VHC595 8-Bit Shift Register with Output Latches Timing Diagram (c)1993 Fairchild Semiconductor Corporation 74VHC595 Rev. 1.2 www.fairchildsemi.com 3 74VHC595 8-Bit Shift Register with Output Latches Logic Diagram (positive logic) (c)1993 Fairchild Semiconductor Corporation 74VHC595 Rev. 1.2 www.fairchildsemi.com 4 74VHC595 8-Bit Shift Register with Output Latches Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC VIN VOUT IIK IOK IOUT ICC TSTG TL Supply Voltage DC Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current DC VCC / GND Current Storage Temperature Parameter Rating -0.5V to +7.0V -0.5V to +7.0V -0.5V to VCC + 0.5V -20mA 20mA 25mA 75mA -65C to +150C 260C Lead Temperature (Soldering, 10 seconds) Recommended Operating Conditions(1) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VIN VOUT TOPR t r, t f Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 3.3V 0.3V VCC = 5.0V 0.5V Parameter Rating 2.0V to +5.5V 0V to +5.5V 0V to VCC -40C to +85C 0 100ns/V 0 20ns/V Note: 1. Unused inputs must be held HIGH or LOW. They may not float. (c)1993 Fairchild Semiconductor Corporation 74VHC595 Rev. 1.2 www.fairchildsemi.com 5 74VHC595 8-Bit Shift Register with Output Latches DC Electrical Characteristics TA = 25C Symbol Parameter VIH VIL VOH HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage TA = -40C to +85C Max. Min. 1.50 0.7 x VCC 0.50 0.50 0.3 x VCC 1.9 2.9 4.4 2.48 3.80 V V VCC (V) Conditions 2.0 3.0 - 5.5 2.0 3.0 - 5.5 2.0 3.0 4.5 3.0 4.5 VIN = VIH or VIL IOH = -4mA IOH = -8mA IOL = 50A VIN = VIH or VIL IOH = -50A Min. 1.50 0.7 x VCC Typ. Max. Units V 0.3 x VCC 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 IOL = 4mA IOL = 8mA VIN = VCC or GND, VOUT = VCC or GND, VING = VIH or VIL VIN = 5.5V or GND VIN = VCC or GND 0.1 0.1 0.1 0.36 0.36 0.25 2.0 3.0 4.5 VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 0.1 0.1 0.1 0.44 0.44 2.5 V IOZ 3-STATE Output Off-State Current Input Leakage Current Quiescent Supply Current 5.5 A IIN ICC 0 - 5.5 5.5 0.1 4.0 1.0 40.0 A A Noise Characteristics TA = 25C Symbol VOLP (2) Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage VCC (V) 5.0 5.0 5.0 5.0 Conditions CL = 50pF CL = 50pF CL = 50pF CL = 50pF Typ. 0.9 -0.9 Limits 1.2 -1.2 3.5 1.5 Units V V V V VOLV(2) VIHD(2) VILD(2) Note: 2. Parameter guaranteed by design. (c)1993 Fairchild Semiconductor Corporation 74VHC595 Rev. 1.2 www.fairchildsemi.com 6 74VHC595 8-Bit Shift Register with Output Latches AC Electrical Characteristics TA = +25C Symbol tPLH, tPHL TA = -40C to +85C Min. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 70 50 115 85 1.5 1.0 1.5 1.0 10 pF pF pF ns MHz Parameter Propagation Delay Time, RCK to QA-QH VCC (V) 3.3 0.3 Conditions CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF RL = 1k CL = 15pF CL = 50pF CL = 15pF CL = 50pF RL = 1k CL = 50pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF (3) Min. Typ. 7.7 10.2 5.4 6.9 8.8 11.3 6.2 7.7 8.4 10.9 5.9 7.4 7.5 9.0 4.8 8.3 12.1 7.6 Max. 11.9 15.4 7.4 9.4 13.0 16.5 8.2 10.2 12.8 16.3 8.0 10.0 11.5 15.0 8.6 10.6 15.7 10.3 Max. 13.5 17.0 8.5 10.5 15.0 18.5 9.4 11.4 13.7 17.2 9.1 11.1 13.5 17.0 10.0 12.0 16.2 11.0 Units ns 5.0 0.5 ns tPLH, tPHL Propagation Delay Time, SCK-Q'H 3.3 0.3 ns 5.0 0.5 ns tPHL Propagation Delay Time, SCLR -Q'H 3.3 0.3 ns 5.0 0.5 ns tPZL, tPZH Output Enable Time, G to QA-QH 3.3 0.3 ns 5.0 0.5 ns tPLZ, tPHZ fMAX Output Disable Time, G to QA-QH Maximum Clock Frequency 3.3 0.3 5.0 0.5 3.3 0.3 ns 80 55 135 95 150 130 185 155 MHz 5.0 0.5 tOSLH, tOSHL CIN COUT CPD Output to Output Skew 3.3 0.3 5.0 0.5 CL = 50pF CL = 50pF 5.0 6.0 87 Input Capacitance Output Capacitance Power Dissipation Capacitance VCC = Open VCC = 5.0V (4) 10 Notes: 3. Parameter guaranteed by design. tOSLH = | tPLH max - tPLH min|; tOSHL = | tPHL max - tPHL min| 4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (Opr.) = CPD * VCC * fIN + ICC (c)1993 Fairchild Semiconductor Corporation 74VHC595 Rev. 1.2 www.fairchildsemi.com 7 74VHC595 8-Bit Shift Register with Output Latches AC Operating Requirements TA = 25C Symbol tS tS tS tH tH tH tW(L) TA = -40C to +85C 3.5 3.0 8.5 5.0 9.0 5.0 1.5 2.0 0.0 0.0 0.0 0.0 5.0 5.0 5.0 5.0 5.0 5.0 3.0 2.5 ns ns ns ns ns ns ns ns ns ns Parameter Minimum Setup Time (SER-SCK) Minimum Setup Time (SCK-RCK) Minimum Setup Time (SCLR-RCK) Minimum Hold Time (SER-SCK) Minimum Hold Time (SCK-RCK) Minimum Hold Time (SCLR-RCK) Minimum Pulse Width (SCLR) VCC (V) 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 Typ. Guaranteed Minimum Units 3.5 3.0 8.0 5.0 8.0 5.0 1.5 2.0 0.0 0.0 0.0 0.0 5.0 5.0 5.0 5.0 5.0 5.0 3.0 2.5 tW(L), tW(H) Minimum Pulse Width (SCK) tW(L), tW(H) Minimum Pulse Width (RCK) trem Minimum Removal Time (SCLR-SCK) (c)1993 Fairchild Semiconductor Corporation 74VHC595 Rev. 1.2 www.fairchildsemi.com 8 74VHC595 8-Bit Shift Register with Output Latches Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 1. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A (c)1993 Fairchild Semiconductor Corporation 74VHC595 Rev. 1.2 www.fairchildsemi.com 9 74VHC595 8-Bit Shift Register with Output Latches Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 2. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D (c)1993 Fairchild Semiconductor Corporation 74VHC595 Rev. 1.2 www.fairchildsemi.com 10 74VHC595 8-Bit Shift Register with Output Latches Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. 5.000.10 4.55 5.90 4.45 7.35 0.65 4.40.1 1.45 5.00 0.11 12 MTC16rev4 Figure 3. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 (c)1993 Fairchild Semiconductor Corporation 74VHC595 Rev. 1.2 www.fairchildsemi.com 11 74VHC595 8-Bit Shift Register with Output Latches TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx Across the board. Around the world.TM ActiveArrayTM BottomlessTM Build it NowTM CoolFETTM CorePLUSTM CROSSVOLTTM CTLTM Current Transfer LogicTM DOMETM 2 E CMOSTM (R) EcoSPARK EnSignaTM FACT Quiet SeriesTM (R) FACT (R) FAST FASTrTM FPSTM (R) FRFET GlobalOptoisolatorTM GTOTM (R) HiSeCTM i-LoTM ImpliedDisconnectTM IntelliMAXTM ISOPLANARTM MICROCOUPLERTM MicroPakTM MICROWIRETM Motion-SPMTM MSXTM MSXProTM OCXTM OCXProTM (R) OPTOLOGIC (R) OPTOPLANAR PACMANTM PDP-SPMTM POPTM (R) Power220 (R) Power247 PowerEdgeTM PowerSaverTM Power-SPMTM (R) PowerTrench Programmable Active DroopTM (R) QFET QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM ScalarPumpTM SMART STARTTM (R) SPM STEALTHTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TCMTM (R) The Power Franchise TM TinyBuckTM (R) TinyLogic TINYOPTOTM TinyPowerTM TinyWireTM TruTranslationTM SerDesTM (R) UHC UniFETTM VCXTM WireTM TinyBoostTM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD'S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Preliminary Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I27 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. No Identification Needed Full Production Obsolete Not In Production (c)1993 Fairchild Semiconductor Corporation 74VHC595 Rev. 1.2 www.fairchildsemi.com 12 |
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